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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit pd23c64040bl 64m-bit mask-programmable rom 8m-word by 8-bit (byte mode) / 4m-word by 16-bit (word mode) page access mode data sheet document no. m15277ej2v0ds00 (2nd edition) date published july 2001 ns cp (k) printed in japan description the pd23c64040bl is a 67,108,864 bits mask-programmable rom. the word organization is selectable (byte mode : 8,388,608 words by 8 bits, word mode : 4,194,304 words by 16 bits). the active levels of oe (output enable input) can be selected with mask-option. the pd23c64040bl is packed in 48-pin plastic tsop (i). features ? word organization 8,388,608 words by 8 bits (byte mode) 4,194,304 words by 16 bits (word mode) ? page access mode byte mode : 8 byte random page access word mode : 4 word random page access ? operating supply voltage : v cc = 2.7 to 3.6 v operating supply voltage access time / page access time power supply current (active mode) standby current (cmos level input) v cc ns (max.) ma (max.) a (max.) 3.3 v 0.3 v 90 / 25 65 30 3.0 v 0.3 v 100 / 25 55 30 ordering information part number package pd23c64040blgy- xxx-mjh pd23c64040blgy- xxx-mkh 48-pin plastic tsop (i) (12 18) (normal bent) 48-pin plastic tsop (i) (12 18) (reverse bent) (xxx : rom c ode suffix no.)
data sheet m15277ej2v0ds 2 pd23c64040bl pin configurations (marking side) /xxx indicates active low si gnal. 48-pin plastic tsop (i) (12 18) (normal bent) [ pd23c64040blgy-xxx-mjh ] word, /byte a16 a15 a14 a13 a12 a11 a10 a9 a8 a19 a21 a20 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 /ce gnd gnd o15, a ? 1 o7 o14 o6 o13 o5 o12 o4 v cc v cc nc o11 o3 o10 o2 o9 o1 o8 o0 /oe, oe, dc gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a0 - a21 : address inputs o0 - o7, o8 - o14 : data outputs o15, a ? 1 : data output 15 (word mode), lsb address input (byte mode) word, /byte : mode select /ce : chip enable /oe, oe : output enable v cc : supply voltage gnd : ground nc note : no connection dc : don?t care note some signals can be applied because this pin is not connected to the inside of the chip. remark refer to package drawings for the 1-pin index mark.
data sheet m15277ej2v0ds 3 pd23c64040bl 48-pin plastic tsop (i) (12 18) (reverse bent) [ pd23c64040blgy-xxx-mkh ] word, /byte a16 a15 a14 a13 a12 a11 a10 a9 a8 a19 a21 a20 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 /ce gnd gnd o15, a ? 1 o7 o14 o6 o13 o5 o12 o4 v cc v cc nc o11 o3 o10 o2 o9 o1 o8 o0 /oe, oe, dc gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a0 - a21 : address inputs o0 - o7, o8 - o14 : data outputs o15, a ? 1 : data output 15 (word mode), lsb address input (byte mode) word, /byte : mode select /ce : chip enable /oe, oe : output enable v cc : supply voltage gnd : ground nc note : no connection dc : don ? t care note some signals can be applied because this pin is not connected to the inside of the chip. remark refer to package drawings for the 1-pin index mark.
data sheet m15277ej2v0ds 4 pd23c64040bl input / output pin functions pin name input / output function word, /byte input the pin for switching word mode and byte mode. high level : word mode (4m-word by 16-bit) low level : byte mode (8m-word by 8-bit) a0 to a21 (address inputs) input address input pins. a0 to a21 are used differently in the word mode and the byte mode. word mode (4m-word by 16-bit) a0 to a21 are used as 22 bits address signals. byte mode (8m-word by 8-bit) a0 to a21 are used as the upper 22 bits of total 23 bits of address signal. (the least significant bit (a ? 1) is combined to o15.) o0 to o7, o8 to o14 (data outputs) output data output pins. o0 to o7, o8 to o14 are used differently in the word mode and the byte mode. word mode (4m-word by 16-bit) the lower 15 bits of 16 bits data outputs to o0 to o14. (the most significant bit (o15) combined to a ? 1.) byte mode (8m-word by 8-bit) 8 bits data outputs to o0 to o7 and also o8 to o14 are high impedance. o15, a ? 1 (data output 15, lsb address input) output, input o15, a ? 1 are used differently in the word mode and the byte mode. word mode (4m-word by 16-bit) the most significant output data bus (o15). byte mode (8m-word by 8-bit) the least significant address bus (a ? 1). /ce (chip enable) input chip activating signal. when the oe is active, output states are following. high level : high impedance low level : data out /oe, oe, dc (output enable, don't care) input output enable signal. the active level of oe is mask option. the active level of oe can be selected from high active, low active and don ? t care at order. v cc ? supply voltage gnd ? ground nc ? not internally connected (the signal can be connected).
data sheet m15277ej2v0ds 5 pd23c64040bl block diagram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 o15, a ? 1 word, /byte /oe, oe, dc /ce output buffer y-selector memory cell matrix 4,194,304 words by 16 bits / 8,388,608 words by 8 bits address input buffer x-decoder logic/input input buffer y-decoder a19 o14 o13 o12 o11 o10 o9 o8 o0 o1 o2 o3 o4 o5 o6 o7 a20 a21
data sheet m15277ej2v0ds 6 pd23c64040bl mask option the active levels of output enable pin (/oe, oe, dc) are mask programmable and optional, and can be selected from among "0" "1" " " shown in the table below. option /oe, oe, dc oe active level 0/oel 1oeh dc don ? t care operation modes for each option are shown in the tables below. operation mode (option : 0) /ce /oe mode output state l l active data out h high impedance h h or l standby high impedance operation mode (option : 1) /ce oe mode output state l l active high impedance h data out h h or l standby high impedance operation mode (option : ) /ce dc mode output state l h or l active data out h h or l standby high impedance remark l : low level input h : high level input
data sheet m15277ej2v0ds 7 pd23c64040bl electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc ? 0.3 to +4.6 v input voltage v i ? 0.3 to v cc + 0.3 v output voltage v o ? 0.3 to v cc + 0.3 v operating ambient temperature t a ? 10 to +70 c storage temperature t stg ? 65 to +150 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. capacitance (t a = 25 c) parameter symbol test condition min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o 12 pf dc characteristics (t a = ? ? ? ? 10 to +70 c, v cc = 2.7 to 3.6 v) parameter symbol test condition min. typ. max. unit high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il v cc = 3.0 v 0.3 v ? 0.3 +0.5 v v cc = 3.3 v 0.3 v ? 0.3 +0.8 high level output voltage v oh i oh = ? 100 a2.4v low level output voltage v ol i ol = 2.1 ma 0.4 v input leakage current i li v i = 0 v to v cc ? 10 +10 a output leakage current i lo v o = 0 v to v cc , chip deselected ? 10 +10 a power supply current i cc1 /ce = v il (active mode), v cc = 3.0 v 0.3 v 55 ma i o = 0 ma v cc = 3.3 v 0.3 v 65 standby current i cc3 /ce = v cc ? 0.2 v (standby mode) 30 a
data sheet m15277ej2v0ds 8 pd23c64040bl ac characteristics (t a = ? ? ? ? 10 to +70 c, v cc = 2.7 to 3.6 v) parameter symbol test condition v cc = 3.0 v 0.3 v v cc = 3.3 v 0.3 v unit min. typ. max. min. typ. max. address access time t acc 100 90 ns page access time t pac 25 25 ns chip enable access time t ce 100 90 ns output enable access time t oe 25 25 ns output hold time t oh 00ns output disable time t df 0 25 0 25 ns word, /byte access time t wb 100 90 ns remark t df is the time from inactivation of /ce or /oe, oe to high-impedance state output. ac test conditions input waveform (rise / fall time 5 ns) output waveform output load 1 ttl + 100 pf test points 1.4 v 1.4 v test points 1.4 v 1.4 v
data sheet m15277ej2v0ds 9 pd23c64040bl read cycle timing chart 1 a0 to a21, a ? 1 note 1 (input) o0 to o7, o8 to o15 note 3 (output) /ce (input) /oe, oe (input) t acc t ce t oe t df note 2 t oh data out high impedance notes 1. during word mode, a ? 1 is o15. 2. t df is specified when one of /ce, /oe, oe is inactivated. 3. during byte mode, o8 to o14 are high impedance and o15 is a ? 1.
data sheet m15277ej2v0ds 10 pd23c64040bl read cycle timing chart 2 (page access mode) a2 to a21 (input) /ce (input) /oe, oe (input) t acc data out t ce t oe t pac note 4 t pac note 4 o0 to o7, o8 to o15 note 3 a ? 1, note 1 a0, a1 (input) (output) data out data out high impedance high impedance t oh t oh t oh t df note 2 notes 1. during word mode, a ? 1 is o15. 2. t df is specified when one of /ce, /oe, oe is inactivated. 3. during byte mode, o8 to o14 are high impedance and o15 is a ? 1. 4. the definitions of page access time is as follows. page access time upper address (a2 to a22) inputs condition /ce input condition /oe, oe input condition t pac before t acc ? t pac before t ce ? t pac before stabilizing of page address (a ? 1, a0, a1)
data sheet m15277ej2v0ds 11 pd23c64040bl word, /byte switch timing chart data out a ? 1 (input) word, /byte (input) high impedance high impedance data out data out high impedance o0 to o7 (output) o8 to o15 (output) t oh t acc t oh t wb data out data out t df remark /oe, oe and /ce : active.
data sheet m15277ej2v0ds 12 pd23c64040bl package drawings notes 48-pin plastic tsop( i ) (12x18) item millimeters a b c e i 12.0 0.1 0.5 (t.p.) 0.1 0.05 0.45 max. k 1.2 max. 16.4 0.1 0.145 0.05 f 0.10 m d 0.22 0.05 1. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 2. "a" excludes mold flash. (includes mold flash : 12.4 mm max.) r k l 1.0 0.05 g l 0.5 0.10 n p 18.0 0.2 q3 + 5 ? 3 0.25 r s48gy-50-mjh1-1 s 0.60 0.15 j 0.8 0.2 s q s n e g f j detail of lead end c d m m b a i p 1 24 48 25 s
data sheet m15277ej2v0ds 13 pd23c64040bl 0.145 0.05 notes 48-pin plastic tsop( i ) (12x18) item millimeters a b c e i 12.0 0.1 0.5 (t.p.) 0.1 0.05 0.45 max. k 1.2 max. 16.4 0.1 f 0.10 m d 0.22 0.05 1. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 2. "a" excludes mold flash. (includes mold flash : 12.4 mm max.) c b r k d m m 1.0 0.05 g l 0.5 0.10 n p 18.0 0.2 q3 + 5 ? 3 0.25 r s48gy-50-mkh1-1 s 0.60 0.15 j 0.8 0.2 s n j g f l s q e detail of lead end 1 24 48 25 s a i p
data sheet m15277ej2v0ds 14 pd23c64040bl recommended soldering conditions please consult with our sales offices for soldering conditions of the pd23c64040bl. types of surface mount device pd23c64040blgy-mjh : 48-pin plastic tsop (i) (12 18) (normal bent) pd23c64040blgy-mkh : 48-pin plastic tsop (i) (12 18) (reverse bent)
data sheet m15277ej2v0ds 15 pd23c64040bl notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd23c64040bl the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of july, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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